1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method thereof, and more specifically, a semiconductor device suitable for mixed mounting high-voltage MOS (Metal Oxide Semiconductor) transistors and low-voltage MOS transistors, and a manufacturing method thereof.
2. Description of the Related Art
In forming a plurality of MOS transistors on the same semiconductor substrate, an element isolation region made of an oxide film or the like is provided between neighboring transistors to insulate them from each other. Also, below the element isolation region is provided a channel stopper region comprising an impurity region of the same conduction type as a well region.
In terms of construction, if the channel stopper region is formed contacting a high-concentration impurity region comprising a source region or a drain region of an MOS transistor, when the transistor is in the operating state, a reverse bias is applied to a pn-junction formed in the contact section. That is to say, an electric field is concentrated in the pn-junction, and degradation of the reverse characteristic occurs such as a decrease in a breakdown voltage. Therefore, adopted in high-voltage MOS transistors is a structure wherein a specified interval (offset region) is provided between the channel stopper region and the high concentration impurity region so that they do not directly contact each other. However, if an offset region is immediately below the gate electrode, when an operation potential is applied to the gate electrode, a reverse layer is also formed in the region, causing a current leak to flow via the region between the source region and the drain region (hereafter referred to as a source-drain leak).
As a measure to prevent this, Japanese Patent No. 2800702 proposes an MOS transistor which adopts the offset structure described above and which can prevent a source-drain leak immediately below the gate electrode. FIGS. 11A to 11C are diagrams showing the structure of such a conventional n-channel MOS transistor. FIG. 11A is a plain layout diagram of an MOS transistor, and FIGS. 11B and 11C are cross-sectional views along the A-A line and the B-B line.
As shown in FIGS. 11A to 11C, the MOS transistor disclosed in Japanese Patent No. 2800702 is provided with a field oxide film 103 for element isolation at the surface portion of a p-type well region 102 (hereafter referred to as a p-well 102) formed on an n-type silicon substrate 101. Formed at the surface portion of the p-well 102 in a region sectioned by the field oxide film 103 are a source region and a drain region of an LDD (Lightly Doped Drain) structure in positions opposing each other across a gate electrode 105 formed on a gate oxide film 104. In this instance, the source region and the drain region are constructed of an n-type low concentration impurity region 106 (hereafter referred to as a low concentration region 106) and a high concentration impurity region 107 (hereafter referred to as a high concentration region 107).
A channel stopper region 108 comprising a p-type impurity region is also formed below the field oxide film 103. The channel stopper region 108 is placed via an offset region 109 in regions excluding that immediately below the gate electrode 105, owing to which the channel stopper region 108 never directly makes contact with the source region or the drain region.
On the other hand, immediately below the gate electrode 105 the channel stopper region 108 is formed projecting toward an element region 111, contacting a channel region 110 (see FIG. 11C). In this instance, it is desirable that the surface concentration of the channel stopper region 108 be lower than the surface concentration of the high concentration region 107 and higher than the surface concentration of the low concentration region 106.
According to such construction, because the channel stopper region 108 is provided with an offset region 109 provided relative to the high concentration region 107 and the low concentration region 106, and can obtain the effect of an offset structure described above. Because the channel stopper region 108 makes contact with the channel region 110 immediately below the gate electrode 105, no reverse layer occurs in regions adjoining the channel region 110, preventing the occurrence of a source-drain leak.
From the standpoint of realizing a high-voltage MOS transistor, as shown in the cross-sectional view in FIG. 12, an MOS transistor is provided (shown in FIG. 12 is an n-channel type) having a structure which has a field oxide film 120 at the channel ends in the gate length direction, and a field limiting region 121, formed below the field oxide film 120, comprising a impurity region with an opposite conduction type to the well region 102. With this structure, because the field limiting region 121 can limit the electric field concentrated at the channel ends of the drain region, an MOS transistor having a very high breakdown voltage can be realized.